`include "cpu_def.vh"

module hi_lo_forward(
  input [ 1:0] de_hl_raddr,
  input [ 1:0] ex_hl_wen  ,
  input [63:0] ex_hl_wdata,
  input [ 1:0] wb_hl_wen  ,
  input [63:0] wb_hl_wdata,

  output [ 1:0] sel_hl_rdata ,  // select hl read data in de stage
                                //* 00: read from hi lo
                                //* 01: ex hl write data
                                //* 10: wb hl write data
  output [31:0] hl_rdata_ex,
  output [31:0] hl_rdata_wb
);

  wire de_ex_rel = |(de_hl_raddr & ex_hl_wen);
  wire de_wb_rel = |(de_hl_raddr & wb_hl_wen);

  assign sel_hl_rdata[0] = de_ex_rel;
  assign sel_hl_rdata[1] = de_wb_rel && !de_ex_rel;

  assign hl_rdata_ex = {32{de_hl_raddr[0]}} & ex_hl_wdata[31: 0] |
                       {32{de_hl_raddr[1]}} & ex_hl_wdata[63:32] ;
  assign hl_rdata_wb = {32{de_hl_raddr[0]}} & wb_hl_wdata[31: 0] |
                       {32{de_hl_raddr[1]}} & wb_hl_wdata[63:32] ;
endmodule